In general, magnetic recording devices like a digital VCR process data in parallel. In recording, the parallel data are converted to serial data after providing with synchronous signals. In reproduction, the serial data is converted to parallel data, when the continuously reproduced serial data is required to be converted to parallel data on time in order to obtain the exact original parallel data from the converted serial data. If the converting time were mismatched, the converted parallel data will be different with the original data. For example, if the serial data were converted to parallel data one clock earlier, the least significant bit of the converted data become the most significant bit of the next parallel data. Because the matching of converting time is very important as explained above, the synchronous signal having been provided on recording are detected to use as a basis.
Shown in FIG. 1 is a block diagram for conventional device for converting data from series to parallel. The device includes a shift register 10 for shifting the input serial data as many as the number of bits of the synchronous signal patterns according to the serial clock, a synchronous signal detector 20 for detecting synchronous signal from signals by means of logical combination of output signals of the shift register 10, parallel data clock generator 30 for generating base signals being pulses in 8-bit interval and the parallel data clock according to the synchronous signal detected at the synchronous signal detector 20, and parallel shift register 40 for converting the output from the shift register 10 to parallel data according to the base signals generated in the parallel data clock generator 30.
The device for converting data from series to parallel shown in FIG. 1 employs a 16 bit shift register 10 to detect 16 bit synchronous signal. In general, in recording of data on tape, data are recorded in synchronous block units, and one synchronous block includes 100 8-bit parallel data as shown in FIG. 2(A), two of which have two synchronous signal pattern(16-bit) while the rest 98 have data pattern.
The 16-bit shift register 10 shifts the serial data reproduced continuously from magnetic tape (not shown) according to the serial data clock, the synchronous signal detector 20 detects synchronous signal by means of logical combination of the shifted output Q1 to Q16 of the shift register 10, the parallel data clock generator 30 generates the parallel clock required in processing the parallel data and pulses in 8-bit interval, by actuating a 3-bit counter (not shown) in the parallel data clock generator 30 according to the detected synchronous signal and the parallel shift register 40 converts the output of the shift register 10 to 8-bit parallel data according to the pulses of 8-bit interval. The 8-bit parallel data are generated continuously form the first detection of the synchronous signal to the next detection of the signal.
However, it has happened in such conventional circuits cases when correct signals could not be detected due to the damage of tape, the deterioration of signals from prolonged use and the instability of the mechanism. For example, burst errors caused by damage of tape may cause the intervals between synchronous signals to change or the patterns disturbed, and random error also may cause the pattern of the synchronous signal disturbed or other non-synchronous signals to enter as synchronous signals. According to the tape recording pattern as shown in FIG. 2(B), each tracks T1, T2 and T3 has 200 synchronous blocks recorded thereon as shown in FIG. 2(B), for which a few heads in VCR read in the signal thereon running on each tracks one by one alternatively. But cases may happen when an error in any synchronous block due to an mechanical error at the moment of the head alternation may disturb signal patterns and change clock. Especially the starting part and the ending part of the tracks is susceptible to error development in have high probability. Accordingly in cases when correct synchronous signals can not be detected, the time to convert data to parallel will be mismatched to cause the problem of the parallel data obtained through this process being different with the original data.